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Application close date: Applications will be accepted on an ongoing basis until the requisition is closed. At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We're working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our diverse team of problem solvers as we add new chapters to the history of spaceflight! At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We're working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our diverse team of problem solvers as we add new chapters to the history of spaceflight! This role is part of the Lunar Permanence business unit, which develops Blue Origin's lunar mission products. To further Blue Origin's mission of having millions of people living and working in space, we are building sustainable infrastructure for our transport of crew and cargo from Earth to the lunar surface. As part of a diverse and hardworking team, you will participate in verification of FPGA-based solutions within Sustaining Lunar Development program's avionics, guidance, and navigation group. This includes requirements development with design engineers, verification through formal methods, UVM based simulation and on-target testing. Our FPGA team is tightly knit and very collaborative, with a variety of experience and backgrounds. We care about the success of each other and our peers and are very willing to help each other learn and grow. Together we will build high-reliability, safety-critical avionics solutions for our Human Landing System (HLS) vehicle. As such, experience with DO-254 is a plus. We are looking for someone to apply their technical expertise, leadership skills, and dedication to quality to positively impact safe human spaceflight. Passion for our mission and vision is required! Key Responsibilities: Perform requirements-based verification of FPGAs using Universal Verification Methodology (UVM). Create comprehensive verification and validation plan that encompasses functional and system level verification and validation. Develop IP/subsystem/system level testbench and tests to achieve required coverage goals. Document plans and procedures. Write directed and random test cases. Generate reports in support of certification of the design to a high DAL. Qualifications: BS/MS in Electrical Engineering, Computer Engineering or a closely related field of study 3+ years experience verifying FPGAs or ASICSs In-depth experience using RTL simulation tools such as Siemens QuestaSim, ModelSim, or equivalent In-depth knowledge ofSystem Verilog and theUniversal Verification Methodology (UVM). Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc.) from scratch. Understands different types ofcoverage, usage of cover classes, cover points, etc. Experience with predictive testbench components,functional coverageandassertions. Experience withconstrained randomverification. Experience with theRegister Abstraction Layer. Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program Reviewing verification and validation results against the coverage goals. Writing, analyzing and achieving coverage metrics. Experience of debugging skills to narrow down and isolate issue between RTL design and testbench or test case is required. Ability to earn trust, maintain positive and professional relationships, and contribute to a culture of inclusion Must be a U.S. citizen or national, U.S. permanent resident (current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum Desired: