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Space Exploration Technologies Corp. Sr. SoC Design For Test (DFT) Engineer in Redmond, Washington

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.SR. SOC DESIGN FOR TEST (DFT) ENGINEER (STARLINK)Would you like to become part of team developing silicon for Starlink's low earth orbit satellites that deliver broadband connectivity to the people who either do not have access to internet or have spotty connectivity? Come join the team working on silicon projects that are driving more integration, lower power, mixed signal architectures and next generation silicon technology for deployment in space and ground infrastructures.RESPONSIBILITIES: Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) toolsIntegration and verification of Design for Test (DFT) fabrics and IP within SubsystemsRunning and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverageRun ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goalsCreating ATPG content for use in post-silicon testing and validating that content through gate level simulationCollaborate with circuit physical design team, ATPG team and manufacturing team to facilitate high quality scan coverage in siliconBASIC QUALIFICATIONS:Bachelor's degree in electrical engineering, computer engineering, or computer science5+ years of experience working with ASICsExperience in Scan Insertion and DFT setup, integration, and validationPREFERRED SKILLS AND EXPERIENCE:Deep understanding of ASIC design flow, methodologies, physical design, and verificationRTL experience to understand, trace and debug RTL connectivity issues as they pertain to DFTAbility to solve complex problems including clock domain crossings and power optimizationExperience with UPF (Unified Power Format), formal verification, and DRC rule checking experienceFamiliar with advanced silicon process and technology nodes for high speed and low power consumptionExperience with high reliability design and implementationsExcellent scripting skills (csh/bash, Perl, Python etc.)Familiar with implementation or integration of design blocks using Verilog/SystemVerilogAbility to work in a dynamic environment with changing needs and requirementsTeam-player, can-do attitude, and ability to work well in a group environment while still contributing on an individual basisEnjoys being challenged and learning new skillsADDITIONAL REQUIREMENTS:Must be willing to travel when needed (typically Willing to work extended hours and weekends if needed to meet critical milestonesThis position can be based in either Redmond, WA or Irvine, CAITAR REQUIREMENTS:To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR .Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual or