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Microsofts mission is to empower every person and every organization on the planet to achieve more. Join us to achieve this by building the worlds computer. The Artificial Intelligence Silicon Engineering team is seeking passionate, driven, and intellectually curious computer/electrical engineers to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge AI designs that can perform complex and high-performance functions in an extremely efficient manner.

We are looking for a Senior Design Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate must be a highly motivated self-starter who will thrive in this cutting-edge technical environment. You will be part of the design team, driving many facets of high performance, high bandwidth designs.

Responsibilities

In this role you will:

• Establish yourself as an integral member of a digital logic design team for the development of AI components with focus on micro-architectural based functions and features

• Be responsible for the logic design/Register Transfer Level (RTL) entry, design quality (LINT, Change Data Capture (CDC), Remote Desktop Connection (RDC), power etc.) and timing closure of high-performance digital Internet Protocol (IP)

• Collaborate with the verification team to ensure the implementation meets both architectural and micro-architectural intent

• Interface with physical design, design for test, and other teams to optimize tradeoffs within the design

• Provide technical leadership through mentorship and teamwork

Qualifications

Required/Minimum Qualifications

• 7+ years of related technical engineering experience

• OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience

• OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experienceo OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• 6+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog, Design Verification collaboration, and Clock Domain Crossing (CDC)/LINT closure

• 6+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs and Post-Silicon Debug

Other Requirments

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Additional or Preferred Qualifications

• 7+ years of industry experience in logic design with a proven track record of delivering complex solutions

• Working knowledge of writing assertions, coverage and formal verification

• Familiarity with Lint, System Design Constraints (SDC), RDC and CDC tools and methodologies

• Knowledge of verification and debug principles, testbenches, Universal Verification Methodology (UVM), and coverage

• Knowledge in at least one of: high-speed and low-power logic design, fixed- and floating-point arithmetic, fabric and interconnect, high concurrency memory scheduler, data signal processing, Direct Memory Access (DMA), Power, Performance, Area (PPA) tradeoff, etc.

• Knowledge of industry standard bus interfaces such as Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) protocols

• Scripting languages such as Zsh, Bash, Python or Perl

• Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $112,000 - $218,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $145,800 - $238,600 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .