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Job Description

Come and join one of the largest semiconductor companies in the world. Design Enablement (DE) is looking for a SOC Design Engineer.

SOC Design Engineer oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs.

Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from high level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.

Responsibilities will include but not limited:

• Perform and analyze APR results at the partition level or fullchip level through tape-in.

• Close time using construction tools and sign-off STA tools.

• Conduct floorplanning activities including trade-offs in Macro placements, Power Grid definition, and integration requirements.

• Perform DRC and LVS layout verification activities.

• Conduct Power/Performance/Area trade-offs with respect to design optimization.

Qualifications

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field with 5+ years of experience:

• Synopsys or Cadence design (RTL to GDS) tools

• Synopsys-Primetime and PTPX for power analysis

• ICV or Calibre DRC/LVS Layout cleanup

• Physical and functional verification

• EM/IR analysis

Preferred Qualifications:

• Experience with RTL/Logic design Verilog, VCS, etc.

• Coding both UPF and timing constraints files for both partition and SoC level

• Strong analytical ability, problem solving and communication skills

• Ability to work independently and at various levels of abstraction

• Experience in Perl, TCL/Tk programming

• Experience with TFM (Tools, Flows, Methodology) Development

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Covid Statement

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.